1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication, and more specifically, to a method of improving via contact coverage in an integrated circuit.
2. Description of Relevant Art
Integrated circuits are made up of literally millions of active devices formed in or on a silicon substrate or well. The active devices are interconnected together in order to form functional circuits and components from the devices. The devices are interconnected together through the use of multi-level interconnects. A cross-sectional illustration of a typical multilevel interconnect is shown in FIG. 1. Interconnect structures normally have a first level of metalization or interconnect layer 102 (typically aluminum alloys or tungsten), a second level of metalization 104, and sometimes a third or even fourth level of metalization. Interlevel dielectrics 106 (ILD's) such as silicon dioxide (SiO.sub.2) are used to electrically isolate different levels of metalization and the silicon substrate or well 108. The electrical connections between different interconnect levels are made through the use of metalized vias 110 formed in ILD 106. In a similar manner, metal contacts 112 are used to form electrical connections between interconnect levels and devices 107 formed in well 108.
In the present invention no distinction is made between "contacts" and "vias" with the term "via" in the present disclosure referring to both contacts and"vias". FIG. 2 shows an overhead view of a portion of an interconnect layer 200. Interconnect layer 200 comprises a plurality of interconnect lines 202 which couple specific metal vias 204 to one another. The individual interconnect lines 202 overlay metal vias 204 and an ILD. The maze-like design or routing of the individual interconnect lines 202 is called the "layout". As would be expected, the layout or placement of individual interconnect lines 202 can be achieved with a variety of different designs. The layout is typically generated by well-known computer aided design techniques. First, design rules are defined. One design rule specifies a minimum distance which must at least exist between any two interconnect lines 202. Another design rule specifies a minimum amount of overlap of vias by overlaying interconnect lines. The specific design rules are generally defined by the manufacturing process utilized. A layout designer attempts to optimize a variety of factors when designing the layout of a specific interconnect level. For example, the interconnect lines 202 are kept as short as possible without adversely effecting the routing of other interconnect lines in the layer. Attempts are also made to prevent routing of interconnect lines in parallel with interconnect lines in layers above and below. The width of the interconnect lines are specified by current carrying requirements with the minimum width of the lines being defined by the process utilized to manufacture the circuit. Vias or contacts are completely covered by respective interconnect lines. It is to be appreciated that although all vias are covered by respective interconnect lines, all vias are not necessarily overlapped. Once the layout has been designed, a mask with the layout or interconnect pattern in it is generated with well-known techniques.
The mask is used along with standard photolithography techniques to form interconnect layer 200 in a semiconductor integrated circuit. First a metal layer, such as aluminum, is blanket deposited over an entire wafer surface. After the metal layer has been formed, a photoresist layer is formed over it. The photoresist layer is then exposed with a mask having the desired interconnect pattern. Those portions of the photoresist layer not covered by the pattern contained in the mask become exposed to light. Portions of the photoresist layer not exposed to light are then developed away, leaving a photoresist pattern which is nearly identical to that which was contained in the mask. Next, the blanket deposited metal layer is etched with an anisotropic etch so that the metal layer becomes patterned with the same pattern as generated in the photoresist, which in turn was generated from the mask.
A problem with the prior art method of laying out an interconnect layer is the amount of via coverage (overlapping) by overlaying interconnect lines. That is, all interconnect lines are designed to cover vias but not necessarily overlap them. For example, as can be seen in FIG. 2, with the prior art layout scheme some vias 204a are overlapped on all four sides. Other vias, for example 204b, are overlapped on three sides and flush with the interconnect line on the fourth. Still other vias, for example 204c, are overlapped on two sides and flush with the interconnect line on two sides. And still other vias, for example 204d, are overlapped on only a single side, and are flush with the interconnect line on the other three. The CAD tool which generates the layout is concerned with optimizing the characteristics listed above and only guarantees that a via will be covered, but not necessarily overlapped. Those vias which are not overlapped on all four sides are more susceptible to reliability and performance (higher resistance) problems in the fabricated integrated circuit. For example, FIG. 3a shows the positioning of an interconnect line 300 over a via 302. Interconnect line 300 is designed to overlap via 302 on three sides but not on the fourth side 303. Due to mask alignment tolerances and/or mask misalignments, the positioning of interconnect line 300 can be shifted in one direction or the other during fabrication of the interconnect layer, as shown in FIG. 3b. If the shift is in a direction away from the side 303 of via 302 which is not overlapped by the interconnect line 300, via 302 will only be partially covered by interconnect line 300.
If the mask is slightly shifted a structure such as shown in FIG. 3c can result. The patterned photoresist layer 304, which is used to mask the metal layer 306, is shifted so that photoresist layer 304 only partially covers metal via 308. As a result, as shown in FIG. 3d, when metal layer 306 is anisotropically etched into individual metal line 307, metal via 308 Can be attacked and entirely or partly etch away. If, due to process marginality, the via is entirely etched away, no electrical connection is made between interconnect lines, resulting in an open circuit and circuit failure. If via 308 is partially etched away, the contact resistance increases because there is less conductor to pass current. An increase in contact resistance will increase the interconnects RC delay which adversely affects circuit performance (i.e. speed). Additionally, a partially etched via is especially troublesome because the circuit may pass all reliability tests yet still fail after testing is complete and the product sold.
Thus, what is needed is a method to improve the coverage of a via or contact by an interconnect line so that potential manufacturing and performance problems are decreased.